1. Field of the Invention
The present invention relates to testing of network devices such as integrated network switches configured for switching data packets between subnetworks.
2. Background Art
Local area networks use a network cable or other media to link stations on the network. Each local area network architecture uses a media access control (MAC) enabling network interface devices at each network node to access the network medium.
Switched local area networks are encountering increasing demands for higher speed connectivity, more flexible switching performance, and the ability to accommodate more complex network architectures. For example, commonly-assigned U.S. Pat. No. 5,953,335 discloses a network switch configured for switching layer 2 type Ethernet (IEEE 802.3) data packets between different network nodes; a received layer 2 type data packet may include a VLAN (virtual LAN) tagged frame according to IEEE 802.1p (802.1D) protocol that enables the network switch to perform more advanced switching operations. For example, the VLAN tag may specify another subnetwork (via a router) or a prescribed group of stations.
Currently, in testing network logic using an emulation system configured for emulating a multiport switch having switch ports, the emulation system sends signals to a Central Processing Unit (CPU). Typically, the CPU is operating at a speed much greater than the speed of the emulation system. For example, the CPU may be running at 40 MHz with the emulation system running at 250 KHz. If the multiport switch is running on the CPU clock, a ready (RDY) signal typically is used to signal the presence of valid data on a read/write (R/W) bus during a read operation or the latching of data from the R/W bus during a write operations. However, in the emulation system, the multiport switch is running on a much slower emulation clock. Due to the difference in emulation system and CPU speed, a RDY signal from the emulation system will release the CPU access, causing the CPU to continue to the next instruction even though the emulation system has not completed the access cycle. Hence, the substantial difference in clock rates prevent reliable synchronous operations (e.g., write access or read access) between the CPU and the emulation system, preventing a test designer from testing the emulated system properly.